Side Navigation
X
JEDEC JESD96A-1
Addendum 1 to JESD96A – INTEROPERABILITY AND COMPLIANCE TECHNICAL REQUIREMENTS FOR JEDEC STANDARD JESD96A – RECOMMENDED PRACTICE FOR USE WITH IEEE 802.11N
Amendment by JEDEC Solid State Technology Association, 01/01/2007
JEDEC JESD82-6A
DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 11/01/2004
JEDEC JESD82-3B
DEFINITION OF THE SSTV16857 2.5 V, 14-BIT SSTL_2 REGISTERED BUFFER FOR DDR DIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 11/01/2004
JEDEC JESD22-A113G
PRECONDITIONING OF PLASTIC SURFACE MOUNT DEVICES PRIOR TO RELIABILITY TESTING
standard by JEDEC Solid State Technology Association, 10/01/2015
JEDEC JESD91-A (R2011)
METHOD FOR DEVELOPING ACCELERATION MODELS FOR ELECTRONIC COMPONENT FAILURE MECHANISMS
standard by JEDEC Solid State Technology Association, 08/01/2003
JEDEC JESD 82-12A
DEFINITION OF THE SSTU32S869 & SSTU32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 04/01/2007
JEDEC JEP162
System Level ESD: Part II: Implementation of Effective ESD Robust Designs
standard by JEDEC Solid State Technology Association, 01/01/2013
JEDEC JESD 8-9B
ADDENDUM No. 9B to JESD8 – STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002
standard by JEDEC Solid State Technology Association, 05/01/2002