JEDEC JESD 12-2
ADDENDUM No. 2 to JESD12 – STANDARD FOR CELL-BASED INTEGRATED CIRCUIT BENCHMARK SET
Amendment by JEDEC Solid State Technology Association, 02/01/1986
ADDENDUM No. 2 to JESD12 – STANDARD FOR CELL-BASED INTEGRATED CIRCUIT BENCHMARK SET
Amendment by JEDEC Solid State Technology Association, 02/01/1986
MECHANICAL SHOCK
standard by JEDEC Solid State Technology Association, 11/01/2004
Guidelines for Visual Inspection and Control of Flip Chip Type Components (FCxGA)
standard by JEDEC Solid State Technology Association, 01/01/2013
ADDENDUM No. 1 to JESD35 – GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS
standard by JEDEC Solid State Technology Association, 09/01/1995
SERIAL INTERFACE FOR DATA CONVERTERS
standard by JEDEC Solid State Technology Association, 04/01/2008
Potential Failure Mode and Effects Analysis (FMEA)
standard by JEDEC Solid State Technology Association, 08/01/2018
DESIGNATION SYSTEM FOR SEMICONDUCTOR DEVICES
standard by JEDEC Solid State Technology Association, 02/01/1982
WIRE BOND SHEAR TEST
standard by JEDEC Solid State Technology Association, 04/01/2017
RECOMMENDED PRACTICE FOR MEASUREMENT OF TRANSISTOR LEAD TEMPERATURE
standard by JEDEC Solid State Technology Association, 06/01/2004